Course
Description
Interested in learning how to effectively utilize Virtex®-5 FPGA architectural resources? Targeted towards experienced Xilinx users who have already completed Fundamentals of FPGA Design and Designing for Performance and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device.
Topics covered include a Virtex-5 FPGA overview, the new CLB, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources. The resources available in the LXT and SXT platforms (EMAC, the PCI Express® architecture, and GTP transceivers) are also discussed. In addition, you will learn about the resources included in the FXT platform (GTX transceivers and the PowerPC® processor). A combination of modules and labs allow for practical hands-on application of the principles taught.
Level
- Intermediate
Duration
- 1 day
Why
this training pays huge dividends
After completing this training, you will be able to:
- Describe the 6-input LUT of the Virtex-5 FPGA
- Specify the CLB arrangement in the Virtex-5 FPGA
- Define the block RAM resources of the Virtex-5 FPGA
- Differentiate the arithmetic logic resources of the DSP48E slice in the Virtex-5 FPGA
- Identify the clocking resources of the Virtex-5 FPGA
- Describe the new features of the Virtex-5 LXT, SXT, and FXT
FPGA platform
Software Tools
- Xilinx ISE® Foundation™ 10.1 software
Course Outline
- Introduction
- Virtex-5 FPGA Overview
- CLB Resources
- Clocking Resources
- Lab 1: Clocking Resources
- I/O Resources
- Memory Resources
- XtremeDSP Solution Resources
- Lab 2: DSP48E Resources
- Virtex-5 LXT, SXT, and FXT FPGA Overview
- Lab 3: (Optional) DSP48E Resources
Lab Descriptions
The labs will provide practical hands-on application of the principles taught throughout the course.
Lab 1: Clocking Resources – In this lab, you will use the Architecture Wizard to create a PLL core for instantiation in your design. You will then simulate and verify the PLL core.
Lab 2: DSP48E Resources – In this lab, you will create a MACC and a loadable MACC by using the XtremeDSP™ solution (DSP48E) resource through the CORE Generator™ software. You will then compare the OPMODEs chosen by the CORE Generator software with the expected values.
Lab 3: DSP48E Resources – The DSP48E resource in the Virtex-5 FPGA can also be utilized to create non-DSP functions in order to save slice resources. In this optional lab, you will create a multiplexer by using the XtremeDSP solution (DSP48E) resource through primitive
instantiation. You will then simulate the resources to verify functionality.
Who
Must Attend
For those who have taken the Fundamentals of FPGA Design and Designing for Performance courses. A comprehensive knowledge of the Virtex-4 family architecture is also required. This material should be considered a Virtex-5 FPGA update course from the Virtex-4 FPGA family.
Prerequisites
- Attended "FPGA Design Expert" course
- Attended "Designing with the Virtex-4 Family" course
- Comprehensive knowledge of the Virtex-4 FPGA
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