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Course
Description
Verilog & FPGA Design Expert is a comprehensive training package that comprises of 2 course modules: Comprehensive Verilog, and FPGA Design Expert . Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.
Comprehensive Verilog (3-day) is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001..
FPGA Design Expert (3-day) is specially designed for designers new to FPGAs design or programmable logic. Beginning with the architecture of Xilinx FPGA, the workshop will first provide the essential knowledge required to implement a design successfully using the ISE software tools. The first part of the workshop will give you a headstart on not just a fast design turn, but an elegant design as well. The second part of the workshop shall focus on how to create more efficient designs to enhance overall performance. You will learn how to create a faster design, fit your design into a smaller FPGA or a lower speed grade, thereby reducing your system cost and development time. Plus, you will configure your personal FPGA evaluation board using Xilinx insystem-configuration software, which you may take with you after the workshop. Ultimately, the workshop objective is to groom you into a FPGA Design Expert.
Duration
6 days
Prerequisites
You are required to have basic digital design knowledge as well as at least two months' coding experience is recommended and have attended ‘Comprehensive VHDL’ course or equaivalent skills.
Why
this training pays huge dividends
After completing this training, you will be able to:
Comprehensive Verilog
- Write RTL Verilog code for synthesis
- Write Verilog test fixtures for simulation
- Create a Finite State Machine (FSM) by using Verilog
- Target and optimize Xilinx FPGAs by using Verilog
- Run a timing simulation by using Xilinx Simprim libraries Create and manage designs by using the ISE-software design environment
- Implement Verilog 2001 language enhancements
FPGA Design Expert
- Write HDL code to efficiently target Xilinx devices
- Create customized cores by using the CORE Generator™ software
- Analyze design performance by using timing reports to achieve timing closure
- Make path-specific timing constraints by using the Xilinx Constraints Editor
- Improve design performance and manage software runtime by using timing-driven Map, PAR Extra Effort, and MPPR/re-entrant routing techniques
- Write HDL code to efficiently implement functions in a Xilinx FPGA
- Build reliable circuits for an FPGA
- Use the Architecture Wizard to create DCM instantiations
- Assign pin locations and enter global timing constraints using the Constraints Editor
- Read reports to determine whether design goals were met
- Locate and modify implementation options
Course Outline
Module 1: Comprehensive Verilog
Day 1
- Hardware Modeling Overview
- Verilog Language Concepts
- Memories, Modules, and Ports
- Lab 1: Building Hierarchy
- Introduction to Testbenches
- Lab 2: Verilog Simulation and RTL Verification
- Operators and Expressions
Day 2
- Data Flow-Level Modeling
- Lab 3: Memory
- Verilog Procedural Statements
- Controlled Operation Statements
- Lab 4: n-bit Binary Counter and RTL Verification
- Advanced Language Concepts
- Lab 5: Comparator
Day 3
- Tasks and Functions
- Lab 6: Arithmetic Logic Unit
- Finite State Machines
- Lab 7: Finite State Machine
- Targeting Xilinx FPGAs
- Lab 8: Calculator
Lab Descriptions
The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.
Module 2: FPGA Design Expert
Day 4
- Basic FPGA Architecture
- Lab 1: Xilinx Tool Flow
- Reading Reports
- Lab 2: Architecture Wizard and PACE
- Global Timing Constraints
- Lab 3: Global Timing Constraints
- Implementation Options
- Lab 4: Implementation Options
- Synchronous Design Techniques
Day 5
- Designing with the Digital Clock Manager
- Lab 1: Digital Clock Manager
- FPGA Design Techniques
- Synthesis Techniques
- Lab 2: Synthesis Techniques
- CORE Generator System
- Lab 3: CORE Generator System CPLD Synthesis
Day 6
- Lab 4: FPGA Editor Demo
- Achieving Timing Closure
- Lab 5: Review of Global Timing Constraints
- Timing Groups and OFFSET Constraints
- Path-Specific Timing Constraints
- Lab 6: Achieving Timing Closure
- Advanced Implementation Options
- Power Estimation
- Course Summary
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