VHDL & FPGA Design Expert

Course Description

VHDL & FPGA Design Expert is a comprehensive training package that comprises of 2 course modules:Designing with VHDL, FPGA Design Expert . Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.

Designing with VHDL (3-day) provides a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, Register Transfer Level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.

In this three-day course, you will gain valuable hands-on experience.
Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

FPGA Design Expert (3-day) is specially designed for designers new to FPGAs design or programmable logic. Beginning with the architecture of Xilinx FPGA, the workshop will first provide the essential knowledge required to implement a design successfully using the ISE software tools. The first part of the workshop will give you a headstart on not just a fast design turn, but an elegant design as well. The second part of the workshop shall focus on how to create more efficient designs to enhance overall performance. You will learn how to create a faster design, fit your design into a smaller FPGA or a lower speed grade, thereby reducing your system cost and development time. Plus, you will configure your personal evaluation board using Xilinx in-systemconfiguration software, which you may take with you after the workshop. Ultimately, the workshop objective is to groom you into a FPGA Design Expert.

Duration
6 days

Prerequisites
Basic digital design experience

Recommended RELs

• Architecture Wizard and I/O Planning
• Basic HDL Coding Techniques (part 1 and part 2)
• Virtex-6 & Spartan-6 FPGA HDL Coding Techniques (part 1 and part 2)

Who Should Attend
Digital and ASIC designers who are interested in FPGA design training and want to use VHDL effectively for modeling, design, and synthesis of digital designs and learn to use Xilinx FPGAs.

Why this training pays huge dividends
After completing this training, you will be able to:

Designing with VHDL

• Implement the VHDL portion of coding for synthesis
  • Identify the differences between behavioral and structural coding styles
  • Distinguish coding for synthesis versus coding for simulation
  • Use scalar and composite data types to represent information
  • Use concurrent and sequential control structure to regulate information flow
  • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)
• Simulate a basic VHDL design
  • Write a VHDL testbench and identify simulation-only constructs
• Identify and implement coding best practices
  • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
• Create and manage designs within the ISE software environment
  

FPGA Design Expert

• Take advantage of the primary features of the 7 series FPGAs
• Use the Xilinx Project Navigator to implement and simulate an FPGA design
• Read reports and determine whether your design goals were met
• Use the Clocking Wizard to create MMCM instantiations
• Use the I/O Planner to make good pin assignments
• Use the Xilinx Constraints Editor to enter global timing constraints
• Describe the architectural features of the 7 series FPGAs
• Create and integrate cores into your design flow by using the CORE Generator™ software system
• Describe the clocking features of the 7 series FPGAs and how they can be used to improve performance
• Increase performance by duplicating registers and pipelining
• Increase system reliability by adding an appropriate synchronization circuit
• Describe different synthesis options and how they can improve performance
• Describe a flow for obtaining timing closure
• Pinpoint design bottlenecks by using Timing Analyzer reports
• Apply advanced timing constraints to meet your performance goals
• Use advanced implementation options to increase design performance

Course Outline

Module 1: Designing with VHDL

Day 1

• The "Shape" of VHDL
• Lab 1: Using the Tools
• Documentation in VHDL
• Data Types
• Concurrent Operations
• Lab 2: Using Concurrent Statements
• Processes and Variables
• Lab 3: Designing a Simple Process

Day 2

• Introduction to Testbenches
• ISim Simulation Tool Basics
• Lab 4: Simulating a Simple Design
• Creating Memory
• Lab 5: Building a Dual-Port Memory
• Finite State Machines
• Lab 6: Building a Moore Finite State Machine
• Targeting Xilinx FPGAs
• Lab 7: Xilinx Tool Flow

Day 3

• Loops and Conditional Elaboration
• Lab 8: Using Loops
• Attributes
• Functions and Procedures
• Packages and Libraries
• Lab 9: Building Your Own Package
• Interacting with the Simulation
• Writing a Good Testbench
• Lab 10: Building a Meaningful Testbench

Module 2: FPGA Design Expert

Day 4

• Course Agenda
• Basic FPGA Architecture
• Xilinx Tool Flow
• Lab 1: Xilinx Tool Flow
• Reading Reports
• Lab 2: Clocking Wizard and Pin Assignment
• Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool
• Global Timing Constraints
• Lab 4: Global Timing Constraints
• Synchronous Design Techniques
• Course Summary

Day 5

• Review of Essentials of FPGA Design
  
• Designing with FPGA Resources
  
• CORE Generator Software System
• Basic FPGA Clock Resources
• Virtex-6 and Spartan-6 FPGA Clock Resources
• Lab 5 : Designing with FPGA Resources
• FPGA Design Techniques
• Synthesis Techniques
• Lab 6 : Synthesis Techniques

Day 6

• Achieving Timing Closure
  
• Lab 7 : Review of Global Timing Constraints
• Path-Specific Timing Constraints, Part 1
• Path-Specific Timing Constraints, Part 2
• Lab 8 : Achieving Timing Closure
• Advanced Implementation Options
• Lab 9 : Designing for Performance
• Lab 10 : FPGA Editor Demo (optional)
• ChipScope Pro Software (optional)
• Lab 11 : ChipScope Pro Software (optional)

Lab Descriptions

• Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation.  Implement the design using default software options and  download to a Spartan®-6 FPGA SP605 demo board.
• Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead™ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.
• Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead tool. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow the I/O banking rules.
• Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.
• Lab 5: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool.  Instantiate these cores and other clock resources and implement the design.
  
• Lab 6: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results.
• Lab 7: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.
• Lab 8: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.
• Lab 9: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.
• Lab 10: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.
• Lab 11: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging