VHDL & FPGA Design Expert

Course Description

VHDL & FPGA Design Expert is a comprehensive training package that comprises of 2 course modules:Designing with VHDL, FPGA Design Expert . Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.

Designing with VHDL (3-day) provides a thorough introduction to the VHDL language. The emphasis is on writing RTL and behavioral source code. It addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. It is ideal for engineers who wish to gain a foundation in VHDL and empower with the ability to write efficient hardware designs and perform high-level HDL simulations.

FPGA Design Expert (3-day) is specially designed for designers new to FPGAs design or programmable logic. Beginning with the architecture of Xilinx FPGA, the workshop will first provide the essential knowledge required to implement a design successfully using the ISE software tools. The first part of the workshop will give you a headstart on not just a fast design turn, but an elegant design as well. The second part of the workshop shall focus on how to create more efficient designs to enhance overall performance. You will learn how to create a faster design, fit your design into a smaller FPGA or a lower speed grade, thereby reducing your system cost and development time. Plus, you will configure your personal FPGA evaluation board using Xilinx in-system-configuration software, which you may take with you after the workshop. Ultimately, the workshop objective is to groom you into a FPGA Design Expert.

Duration
6 days

Prerequisites
You are required to have basic digital design knowledge.

Why this training pays huge dividends
After completing this training, you will be able to:

Designing with VHDL

• Implement the VHDL portion of coding for synthesis
  • Identify the differences between behavioral and structural coding styles
  • Distinguish coding for synthesis versus coding for simulation
  • Use scalar and composite data types to represent information
  • Use concurrent and sequential control structure to regulate information flow
  • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)
• Simulate a basic VHDL design
  • Write a VHDL testbench and identify simulation-only constructs
• Identify and implement coding best practices
  • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
• Create and manage designs within the ISE 11.1 software environment

FPGA Design Expert

• Take advantage of the primary features of the Virtex®-5 FPGA
• Use the Xilinx Project Navigator to implement and simulate an FPGA design
• Read reports and determine whether your design goals were met
• Use the Architecture Wizard to create DCM instantiations
• Use the PlanAhead tool and PinAhead to make good pin assignments
• Use the Xilinx Constraints Editor to enter global timing constraints
• Describe a flow for obtaining timing closure
• Describe the architectural features of the Virtex®-5 FPGA
• Describe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performance
• Increase performance by duplicating registers and pipelining
• Increase system reliability by adding an appropriate synchronization circuit
• Describe different synthesis options and how they can improve performance
• Create and integrate cores into your design flow by using the CORE Generator™ software system
• Run behavioral simulation on an FPGA design that contains cores
• Pinpoint design bottlenecks by using the Timing Analyzer reports
• Apply advanced timing constraints to meet your performance goals
• Use advanced implementation options to increase design performance

Course Outline

Module 1: Designing with VHDL

Day 1

• The "Shape" of VHDL
• Lab 1: Using the Tools
• Documentation in VHDL
• Data Types
• Concurrent Operations
• Lab 2: Using Concurrent Statements
• Processes and Variables
• Lab 3: Designing a Simple Process

Day 2

• Introduction to Testbenches
• ISim Simulation Tool Basics
• Lab 4: Simulating a Simple Design
• Creating Memory
• Lab 5: Building a Dual-Port Memory
• Finite State Machines
• Lab 6: Building a Moore Finite State Machine
• Targeting Xilinx FPGAs
• Lab 7: Xilinx Tool Flow

Day 3

• Loops and Conditional Elaboration
• Lab 8: Using Loops
• Attributes
• Functions and Procedures
• Packages and Libraries
• Lab 9: Building Your Own Package
• Interacting with the Simulation
• Writing a Good Testbench
• Lab 10: Building a Meaningful Testbench

Module 2: FPGA Design Expert

Day 4

• Basic FPGA Architecture
• Lab 1: Xilinx Tool Flow
• Reading Reports
• Lab 2: Architecture Wizard and PACE
  
• Global Timing Constraints
• Lab 3: Global Timing Constraints
• Implementation Options
• Lab 4: Implementation Options
• Synchronous Design Techniques

Day 5

• Review of Fundamentals of FPGA Design
• Designing with Virtex-4 FPGA Resources
• CORE Generator Software System
• Lab 5: CORE Generator Software System
• Designing Clock Resources
• Lab 6: Designing Clock Resources
• FPGA Design Techniques
• Synthesis Techniques
• Lab 7: Synthesis Techniques

Day 6

• Achieving Timing Closure
• Lab 8: Review of Global Timing Constraints
• Timing Groups and OFFSET Constraints
• Path-Specific Timing Constraints
• Lab 9: Achieving Timing Closure
• Advanced Implementation Options
• Lab 10: Designing for Performance
• Power Estimation (Optional)
• Lab 11: FPGA Editor Demo (Optional)
• ChipScope™ Pro Analyzer (Optional)
• Lab 12: ChipScope Pro Analyzer (Optional)
• Course Summary

Lab Descriptions

• Lab 1 - Xilinx Tool Flow: Create a new project in the ISE Project Navigator and use the Architecture Wizard and PACE tool in the design process. Implement a design using default software options.
• Lab 2 - Architecture Wizard and PACE: Use the Architecture Wizard to customize a DCM, incorporate the DCM into the design, use PACE to assign pin locations, and implement the design.
• Lab 3 - Global Timing Constraints: Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place and Route Static Timing Report to determine the delay of the longest-constrained path for each timing constraint.
• Lab 4 - Implementation Options: Adjust process properties and I/O configuration options to improve design performance.
• Lab 5: CORE Generator Software System – Create a core, instantiate the core into VHDL or Verilog source code, and run behavioral simulation.
• Lab 6: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources.
• Lab 7: Synthesis Techniques – Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software.
• Lab 8: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.
• Lab 9: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.
• Lab 10: Designing for Performance – Improve performance and maximize results solely with implementation options.
• Lab 11: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.
• Lab 12: ChipScope Pro Analyzer – Add an internal logic analyzer to a design to perform real-time debugging