VHDL Design Expert

Course Description
VHDL Design Expert is a comprehensive course that covers the application of VHDL for programmable logic and ASIC design. Based on Xilinx industry standard, this total training package can be considered as the minimum training requirement for project readiness.
The course is based on a 5-day agenda. Comprising 2 modules, it can be taken in two stages by attending the individual modules or the full 5-day training package with an interval of at least 2 months.

Designing with VHDL (3-day) provides a thorough introduction to the VHDL language. The emphasis is on writing RTL and behavioral source code. It addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. It is ideal for engineers who wish to gain a foundation in VHDL and empower with the ability to write efficient hardware designs and perform high-level HDL simulations.

Advanced VHDL (2-day) builds on the foundation to emphasize on advanced coding techniques. This module aims to help engineers to increase their VHDL proficiency for practical projects. It highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs.

Duration
5 days

Prerequisites
It is recommended for you to have basic digital design knowledge with at least two months' coding experience.

Why this training pays huge dividends
After completing this training, you will be able to:

Designing with VHDL

  • Implement the VHDL portion of coding for synthesis
    • Identify the differences between behavioral and structural coding styles
    • Distinguish coding for synthesis versus coding for simulation
    • Use scalar and composite data types to represent information
    • Use concurrent and sequential control structure to regulate information flow
    • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)
  • Simulate a basic VHDL design
    • Write a VHDL testbench and identify simulation-only constructs
  • Identify and implement coding best practices
    • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
  • Create and manage designs within the ISE 11.1 software environment

Advanced VHDL

  • Write efficient and reusable RTL, testbenches, and packages
  • Create self-testing testbenches
  • Create realistic models
  • Use the Text IO capabilities of the VHDL language
  • Store data dynamically
  • Create parameterized designs

Course Outline

Module 1: Designing with VHDL

Day 1

  • The "Shape" of VHDL
  • Lab 1: Using the Tools
  • Documentation in VHDL
  • Data Types
  • Concurrent Operations
  • Lab 2: Using Concurrent Statements
  • Processes and Variables
  • Lab 3: Designing a Simple Process

Day 2

  • Introduction to Testbenches
  • ISim Simulation Tool Basics
  • Lab 4: Simulating a Simple Design
  • Creating Memory
  • Lab 5: Building a Dual-Port Memory
  • Finite State Machines
  • Lab 6: Building a Moore Finite State Machine
  • Targeting Xilinx FPGAs
  • Lab 7: Xilinx Tool Flow

Day 3

  • Loops and Conditional Elaboration
  • Lab 8: Using Loops
  • Attributes
  • Functions and Procedures
  • Packages and Libraries
  • Lab 9: Building Your Own Package
  • Interacting with the Simulation
  • Writing a Good Testbench
  • Lab 10: Building a Meaningful Testbench

Lab Descriptions
The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits.

Module 2: Advanced VHDL

Day 4

  • Course Introduction
  • Modeling and Simulation I: Subprograms and Design Attributes
  • Modeling and Simulation II: Access Types and Blocks
  • Lab 11: Modeling
  • Testbench Stimulus
  • Lab 12: Model Testbench
  • Utilizing Text IO
  • Lab 13: Text IO Testbench

Day 5

  • RTL Design and Xilinx
  • Design Reuse and Parameterized Design
  • Lab 14: RTL and Scalable Design
  • Finite State Machines
  • Lab 15: FSM and Scalable Design
  • Simulation Issues Specific to Xilinx
  • Lab 16: Xilinx and Scalable Design
  • Course Review

Lab Descriptions

  • Lab 11 - Modeling: Write a hardware model utilizing generics, subprograms, generate statements, and access data types.
  • Lab 12 - Model Testbench: Write a self-testing testbench and simulate model.
  • Lab 13 - Text IO Testbench: Utilize VHDL Text IO operations in a self-testing testbench.
  • Lab 14 - RTL and Scalable Design: Write a reusable and scalable design block by utilizing synchronous design techniques.
  • Lab 15 - FSM and Scalable Design: Write a Finite State Machine (FSM) by utilizing FSM techniques for a high-performance FSM.
  • Lab 16 - Xilinx and Scalable Design: Optimize the design for Xilinx implementation. Simulate and implement the optimized design.