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Course
Description
Learn to manage design performance, plan an I/O pin layout, and implement by using the PlanAhead™ software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool.
Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.
Who Should Attend
FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.
Duration
1 day
Why
this training pays huge dividends
After completing this training, you will be able to:
- Use the PlanAhead tool features and benefits
- Import designs into the PlanAhead tool project environment
- Assign I/O pins and clock logic
- Run DRC and SSN noise analysis
- Integrate IP with the PlanAhead tool
- Import HDL sources, elaborate, and analyze the RTL netlist
- Implement the design with different implementation strategies
- Analyze design statistics and timing
- Use the PlanAhead tool integrated with the ISE tool Project Navigator environment
Prerequisites
Software Tools
Xilinx ISE
Course Outline
- PlanAhead Tool Benefits and Features Overview
- PlanAhead Tool Project Manager
- Lab 1: Getting Started with the PlanAhead Tool
- I/O Pin and Clock Planning
- Lab 2: Assigning I/O Pins
- CORE Generator Tool Integration
- Lab 3: CORE Generator Tool Integration
- Project Navigator Integration
- Static Timing Analysis with PlanAhead
- Introduction to the Advanced Design with the PlanAhead Analysis and Design Tool Course
Lab Descriptions
Note: All labs in this course are also available as self-guided tutorials, which are packaged with the PlanAhead software.
- Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.
- Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.
- Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator tool with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.
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