Fundmentals of CPLD & FPGA

Course Description
CPLD and FPGA are becoming a critical part of every system design. There are many different FPGAs with different architectures/ processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? This 2-day course will provide you with the answers and the fundamentals to get started with CPLD and FPGA. It is specially designed for designers new to CPLDS /FPGA design or programmable logic. The course uses Xilinx ISE-series tools to provide students with an introduction to designing with a Xilinx CPLD and implementing a FPGA design.

Duration
2 days

Prerequisites
Digital Designers who have working knowledge of basic HDL (VHDL or Verilog) and who are new to Xilinx CPLDs, FPGAs and/or ISE Tools.

Course Benefits

  • Learn important design practices to ensure the best and most stable
    CPLD & FPGA design
  • Learn how to save costs by fitting designs into smaller devices
  • Reduce time to market by learning how to use the ISE –series software to maximize design performance
  • Increase your productivity by learning

Why this training pays huge dividends
After completing this training, you will be able to:

  • Describe the CPLD tool flow: Design Entry, Synthesis, Implementation, and Programming
  • Understand what products Xilinx offers and where the CoolRunner-II CPLD fits into this offering
  • Recognize the basic architectural resources of the CoolRunner-II CPLD
  • Use Xilinx Project Navigator to implement an FPGA design
  • Assign pin locations with the PACE tool
  • Create DCM instantiations with the Architecture Wizard
  • Use the Constraints Editor to enter basic global timing constraints
  • Locate and modify implementation options

Course Outline

Day 1

  • Course Agenda
  • CoolRunner-II CPLD Architecture
  • CPLD Software Flow
  • Lab 1: Xilinx CPLD Tool Flow
  • Reading CPLD Reports
  • Global Constraints
  • Lab 2: Constraints for CPLDs
  • CPLD Software Options
  • Lab 3: CPLD Implementation Options

Day 2

  • Basic FPGA Architecture
  • Lab 1: Xilinx Tool Flow
  • Reading Reports
  • Lab 2: Architecture Wizard and PACE
  • Global Timing Constraints
  • Lab 3: Global Timing Constraints
  • Implementation Options
  • Lab 4: Implementation Options
  • Synchronous Design Techniques

Lab Descriptions

CPLD:

  • Lab 1 - Xilinx CPLD Tool Flow: Create a new project in the Project Navigator of the ISE software. Implement a design by using default software options and configure the CoolRunner-II CPLD demo board with iMPACT, the Xilinx In-System Programming (ISP) software.
  • Lab 2 - Constraints for CPLDs: Use constraints to specify clock frequencies, pin locations, and I/O standards for the CPLD demo board project. Fit the design and analyze the Timing and Fitter Reports to confirm performance and I/O placement.
  • Lab 3 - Implementation Options: Implement the design with default software options and evaluate the design performance versus design requirements. Apply a global timing constraint for PERIOD to the design. Change the software options and add I/O constraints to meet the design's timing goals.

FPGA:

  • Lab 1 - Xilinx Tool Flow: Create a new project in the ISE Project Navigator and use the Architecture Wizard and PACE tool in the design process. Implement a design using default software options.
  • Lab 2 - Architecture Wizard and PACE: Use the Architecture Wizard to customize a DCM, incorporate the DCM into the design, use PACE to assign pin locations, and implement the design.
  • Lab 3 - Global Timing Constraints: Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place and Route Static Timing Report to determine the delay of the longest-constrained path for each timing constraint.
  • Lab 4 - Implementation Options: Adjust process properties and I/O configuration options to improve design performance.