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Course
Description
This course provides a foundation for Digital Signal Processing (DSP) techniques for Xilinx FPGAs. The course begins with a refresher of basic binary number theory, mathematics, and the essential features within the FPGA that are important to signal processing. The body of the course explores a variety of filter techniques with emphasis on optimal implementation in Xilinx devices and continues with an examination of FFTs, video, and image processing. Throughout the course, Xilinx cores and IP relevant to signal processing are introduced. The course is complemented by hands-on exercises to reinforce the concepts learned.
Level
- Advanced
Duration
- 2 days
Prerequisites
A fundamental understanding of digital signal processing theory, including an understanding of the following principles:
- Sample rates
- Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters
- Oscillators and mixers
- Fast Fourier Transform (FFT) algorithm
Who Must Attend
Engineers and designers interested in DSP design training who have an interest in developing products that use digital signal processing
Why
this training pays huge dividends
After completing this training, you will be able to:
- Describe the advantages of using FPGAs over traditional processors for DSP designs
- Utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
- Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
- Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
- Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA
- Explain the algorithms for video and imaging systems and their implementations in FPGAs
Course Outline
Day 1
- Back to Basics
- Architecture
- FPGA Math
- Exercise 1: Signed Number Conversion, Quantization and Rounding, Adders, Subtractors, and Accumulation
- Shift Registers, RAM, and Applications
- Exercise 2: SRL32E and RAM Estimation and Concatenation
- FIR Filter
- Exercise 3: Filter Implementation, Resource and Performance Estimation
Day 2
- Advanced Filter Techniques
- Exercise 4: Filter Implementations, Resource and Performance Estimation
- Fast Fourier Transform
- Exercise 5: FFT Implementation, Resource and Performance Estimation
- Video and Imaging
- Where Do We Go From Here?
- Demonstration: System Generator and the CORE Generator Tool with a DSP-Targeted Reference Design
- Where Can I Learn More?
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