Verilog HDL for Digital System Design with FPGA

 

Course Highlights
This course covers the use of Verilog HDL in high-level synthesis of digital system designs. The language Verilog HDL as well as how it is used for describing, modeling, simulating and synthesizing various digital modules will be addressed. Verilog HDL coding and synthesis issues on combinational and sequential modules including Finite State Machine will be discussed. In the hands-on sessions, the participants will not only learn the language through hands-on coding, synthesis and simulation of some practical designs, but they will also synthesize and test the designs with industrial software packages and FPGA devices.

Who Must Attend

  • Designers and Engineers who would like to use Verilog HDL for digital system design or would like to gain knowledge on Verilog HDL and high-level synthesis
  • Designers and Engineers who have been working or involving in ASIC design, board-level system design or prototyping with FPGA/CPLD devices
  • Project Managers and Application/Product/Marketing Engineers who would like to gain knowledge on the current design methodology

Course Objectives
Upon completion of the course, participants would have gained solid foundation of:

  • Concept of synthesis
  • Basics of Verilog HDL language, including its use in synthesis of digital designs
  • Verilog HDL coding style for synthesis
  • Design of digital systems with Verilog HDL
  • Modeling Testbench, Simulation and verification of designs with Verilog HDL
  • Industrial-standard design software for coding, synthesis and simulation
  • Hardware implementation of digital systems on FPGA devices

Prerequisites
Digital system or logic design knowledge is preferable.

Course Outline
The 4-day course comprises of lecture sessions on Verilog HDL language, hands-on sessions on coding, synthesis and simulation, together with a fully-guided project and a semi-guided project, in which a complete digital system is coded in Verilog HDL, simulated, synthesized and tested with FPGA devices.

Day 1
Design Hierarchy and Synthesis Concept
Verilog HDL Basics:

Data Types, Module and Port
Structure Description and Continue Assignment
Vector and Array
Operators
Blocking and Non-Blocking Statements
Behvioural Modeling

Testbench:
Concept and Modeling of Testbench
System Tasks for Test Monitoring
Testbench examples


Flow Control Constructs:
Conditional Constructs
Looping Constructs

FPGA Architectures and Features:
FPGA Architectures and Features
FPGA Resources
FPGA vs CPLD

Hands-on:
Coding of Digital Modules in Verilog HDL
Synthesis, Testbench Coding and Simulation
FPGA implementation


Day 2
Verilog for Combinatorial Logic Circuits:
MUX, Decoders and Encoders
Binary Comparator and Parity Checker
Simple ALU, Tri-state Buffer and Bus

Function and Task:
Features and Restrictions
Examples

Memories:
Modeling of ROM, RAM and Dual Port RAM
Memory Initialization

Coding Styles:
Operator Sharing, Expression Grouping and Common Expression
Examples of if-else, case and loop constructs

Hands-on:
Coding, Synthesis and Simulation of Combinational Circuits
RAM Modeling, Initialization and Simulation
Function and Function Call
FPGA Implementation of Combinational Circuits

Day 3
Verilog for Sequential Logic Circuits:
Gated D Latch, Edge-triggered DFF, DFF with Reset
Registers and Shift Registers
Counters

Finite State Machine (FSM):
Moore Machine
Mealy Machine
One-Hot State Assignment

Speed Improvement Techniques:
Pipeline Design
Retiming
Synchronization Circuits


Coding Examples:
Sequence Detector
Serial Multiplier
Handshaking Controller
Traffic Light Controller

Hands-on:
Coding, Synthesis and Simulation of Sequential Circuits
Counter and Debouncing Circuit
Clock Management
FPGA Implementation

Day 4
Guided Project: Design and Implementation of a Complete Digital System
Design of Modules
Verilog Coding of Modules
Simulation and Hardware Verification of Modules
Integration, FPGA Implementation and Hardware Testing of the Complete Design

 

Date:
Please kindly check our Training Calendar
Venue:
  Activemedia Innovation
Time:
  10.00am - 5.30pm
Course Fee:
  Please contact our Training Consultants for details
Enquiries:
6742 8173 enquiry@activemedia.com.sg